1. Field of the Invention
The present invention relates to a method of manufacturing a capacitor and to a method of fabricating semiconductor devices comprising the same. More particularly, the present invention relates to a method of manufacturing a capacitor having a high storage capacitance and to a method of fabricating a semiconductor device comprising the same.
2. Description of the Prior Art
Recently, due to a rapidly increasing and widespread usage of computers, the need for semiconductor devices is expanding. Semiconductor devices having a high storage capacitance and a faster operating speed are now in great demand. To this end, current technology is focused on developing and realizing memory devices having a high degree of integration, response speed, and reliability.
Currently, a dynamic random access memory (DRAM) device which has a high memory capacity and random open input/output functions is widely used as a semiconductor memory device. DRAM devices generally comprise a memory cell region, at which information data is stored in the form of electric charge, and a peripheral circuit for the input/output of data to and from the memory cell region. Furthermore, DRAM devices conventionally include at least one access transistor and a storage capacitor.
Such a storage capacitor must be made smaller and smaller to meet the demand for memory devices having an increasingly higher degree of integration. Accordingly, manufacturing a capacitor having a higher storage capacitance and reduced size is increasingly becoming a challenge. In fact, producing a capacitor having a markedly increased storage capacitance within the same amount of area occupied on a substrate surface by any current storage capacitor is an ever prevailing task.
Generally, capacitance C is represented by the following mathematical expression.
C=xcex50xcex5A/d
In the above expression, xcex50 and xcex5 respectively represent the dielectric constant in a vacuum and a dielectric constant of a dielectric film of a capacitor, while A represents the effective area and d represents the thickness of a dielectric film.
Referring to the above mathematical expression, storage capacitance can be increased by forming the dielectric film from a material having a higher dielectric constant, increasing the effective area of the capacitor, or by decreasing the thickness of the dielectric film.
However, the thickness of a dielectric film can be minimized only to a certain extent in highly integrated memory devices. Furthermore, although a number of dielectric materials having a high dielectric constant and processes of forming a dielectric film utilizing these materials are widely known in the art, processes of forming dielectric films of a material other than a nitride are difficult to incorporate into a mass production method of manufacturing semiconductor devices.
In view of the above, i.e., with respect to the method of manufacturing semiconductor devices, it is easiest to maximize the storage capacitance of a capacitor by maximizing its effective area. For instance, U.S. Pat. No. 5,185,282 discloses a stacked capacitor having the shape of a cup or cylinder, while U.S. Pat. No. 5,656,536 discloses a crown-shaped stacked capacitor, and U.S. Pat. Nos. 5,716,884 and 5,807,782 disclose fin-shaped stacked capacitors.
On the other hand, U.S. Pat. No. 5,877,052 discloses a method of increasing the storage capacitance by forming silicon hemispherical grains (HSG) on a storage electrode. Further, U.S. Pat. No. 5,913,119 discloses a method of forming an HSG layer on a cylindrical storage electrode by combining the above-mentioned techniques.
FIGS. 1A to 1D are sectional views illustrating a method of fabricating a capacitor having a cylindrical storage electrode formed with a silicon HSG layer according to U.S. Pat. No. 5,913,119.
As shown in FIG. 1A, a field oxide layer 3 is formed on a semiconductor substrate 1 for isolating various devices on the substrate 1. A gate oxide layer 5 is formed by thermal oxidation of the active region defined by the field oxide layer 3. Then, a poly-silicon layer 7 and subsequently a silicon oxide layer 9 are formed on the gate oxide layer 5. These layers are then patterned by a photolithography process to thereby yield a gate electrode 11.
Next, an oxide layer is deposited on the surface of substrate 1 adjacent gate electrode 11, and spacers 13 are produced on the side walls of the gate electrode 11 by etching the oxide layer. This process is followed by an ion doping process to form a transistor source/drain region 15.
An insulating interlayer 17 and then a silicon nitride layer 19 are then formed over the substrate 1. Selected portions of the insulating interlayer 17 and silicon nitride layer 19 are then etched to produce a contact hole which exposes the source/drain region 15.
A polysilicon layer is deposited on the silicon nitride layer 19 so as to fill the contact hole. A polysilicon contact 21 is then formed in the contact hole by performing an etch back process.
Next, a cylindrical storage electrode is produced. First, a silicon oxide layer is deposited on the silicon nitride layer 19 and contact 21. Then, utilizing a photolithography process in which a photoresist pattern 27 serves as a mask, the silicon oxide layer is etched to form a silicon oxide layer pattern 23.
As shown in FIG. 1B, after the photoresist pattern 27 is removed, amorphous silicon layers 29, 31, 33, and 35 each having different doped levels of impurities are sequentially formed on silicon nitride layer 19, contact 21, and silicon oxide layer pattern 23. The upper portions of amorphous silicon layers 29, 31, 33, and 35 are then polished by a chemical mechanical polishing (CMP) process. The silicon oxide layer pattern 23 is etched away to yield a cylindrical storage electrode 36.
Referring to FIG. 1C, silicon HSG seeds are deposited on the cylindrical storage electrode 36. Then the seeded storage electrode is subjected to a number of heat treatment processes to grow the seeds and convert amorphous silicon layers 29, 31, and 33 into a silicon HSG layer 37 on the surface of the storage electrode 36.
Referring to FIG. 1D, a dielectric film 39 having an ONO (oxidized-silicon nitride-silicon oxide) structure is formed on the silicon HSG layer 37. Thereafter, a polysilicon plate electrode 41 is formed on the dielectric film 39. An etching process shapes the resultant structure to produce a capacitor 43 comprising storage electrode 36, dielectric film 39, and plate electrode 41.
However, because the above-described process of manufacturing a capacitor attempts to increase the effective area by varying the cylindrical or crown-shaped structural configuration of the capacitor, rather than increasing the surface area of the storage electrode itself, the process faces a fundamental limitation in increasing the storage capacitance. Furthermore, a significant increase in capacitance can hardly be expected compared to the many other variations of cylindrical capacitors known in the art.
Nonetheless some increase in the effective area of the capacitor can be expected by forming a silicon HSG layer on the surface of the storage electrode according to the disclosed method. However, the method is complex, involving the depositing of a number of amorphous silicon layers and a number of heat treatment processes. Accordingly, the prior art method is disadvantageous in that it has low reproducibility and hence, it is associated with high manufacturing costs.
In view of these problems, other methods of forming a storage electrode of a high capacitance capacitor have been developed. One of these methods is as disclosed in U.S. Pat. No. 5,843,822. This patent discloses the use of thermal chemical vapor deposition (thermal CVD) and plasma enhanced chemical vapor deposition (PECVD) to form oxide layers exhibiting a different etching rate from each other when etched by hydrofluoric acid (HF) etchant. Etching the oxide layers at different etching rates produces a wrinkled storage electrode.
FIG. 2 helps illustrate the process of manufacturing a cylindrical capacitor having a wrinkled storage electrode as disclosed in U.S. Pat. No. 5,843,822.
Referring to FIG. 2, a substrate 1 is provided with a source region 53. A first insulating layer 55 of boro-phospho silicate glass (BPSG) is then formed on the substrate 1. Then, the upper portion of the first insulating layer 55 is planarized by utilizing a CMP process.
A second insulating layer 57 of a silicon oxide is then deposited on the planarized first insulating layer 55. Both the first and second insulating layers 55 and 57 are etched to form a contact hole which exposes the source region 53.
A first polysilicon layer 59 is formed on the top portion of the second insulating layer 57 to fill the contact hole. Then, a number of first oxide layers 61 and a number of second oxide layers 63 are alternately formed on the first polysilicon layer 59 by thermal CVD and PECVD methods, respectively. More specifically, first oxide layers 61 each having a thickness of about 200-400 xc3x85 are formed by thermal CVD at a temperature of 750-900xc2x0 C. The second oxide layers 63 each also having a thickness of about 200-400 xc3x85 are formed by PECVD at a temperature of 300-400xc2x0 C.
Portions of the first and second oxide layers 61 and 63 are anistropically etched to form two trenches 67 which extend parallel to each other and expose the first polysilicon layer 59. Then, the exposed side walls of the first and second oxide layers 61 and 63, defining the trenches 67, are subjected to a wet-etching process utilizing hydrofluoric acid HF as the etchant. Due to the different etching rates of the first and second oxide layers 61 and 63, the side walls are etched unevenly and a side wall having a wrinkled or corrugated profile is produced.
A second polysilicon layer is then formed on the side wall and on top of the exposed first polysilicon layer 59. A storage electrode having a wrinkled side wall is produced by then removing the first and second oxide layers 61 and 63.
In the above-described method of manufacturing a capacitor having a wrinkled storage electrode, the effective area of the storage electrode itself is increased. However, because the thermal CVD process is carried out at a temperature of 750-900xc2x0 C. to form the first oxide layers, there is a risk of thermally damaging the transistor and various other components in the active and peripheral circuit regions of the substrate.
In fact, it is well known in the art that using any thermal process in excess of 600xc2x0 C. in manufacturing a semiconductor device imparts thermal damage to the substrate of the device as well as to a myriad of components present on the substrate at the time of the thermal treatment. Thus, it is highly probable that the above-described method, which includes a process carried out at a temperature of about 900xc2x0 C., will produce semiconductor devices exhibiting thermal damage. In fact, in the above described process, thermal damage to the substrate and the various components of the device is inevitable because the thermal CVD process which is required to be carried out at a high temperature is repeated a number of times until a desired height or thickness of oxide layers is achieved.
In view of the above, it is an object of the present invention to provide a method of manufacturing a capacitor having a storage electrode provided with a large surface area which creates a correspondingly high storage capacitance, and which method does not require processes which are carried out at high temperatures.
In order to achieve this object, the method of manufacturing a capacitor of the present invention forms a wrinkled storage electrode using processes which are carried out at no more than about 600xc2x0 C. First, a sacrificial structure is formed on a substrate. The sacrificial structure comprises a number of oxide layers each formed by low pressure CVD or plasma enhanced CVD carried out at about 400-600xc2x0 C. Adjacent ones of the oxide layers exhibit different etching rates when exposed to a predetermined etchant. The different etching rates can be the result of differences in the boron or phosphorous content of the layers or of differences in type or concentration of impurities. At least one hole is formed in the sacrificial structure, whereby a side wall delimiting the hole is produced. The side wall is etched by the etchant, whereby a series of tooth-like prominences and depressions are formed at the side wall. Then, a conductive material is deposited on the side wall to form a storage electrode in which the prominences and depressions of the side wall of the sacrificial structure are reproduced. The sacrificial structure is thereafter removed, whereby the conductive material left remaining constitutes the storage electrode of the capacitor.
A second object of the present invention to provide a method of manufacturing a semiconductor device comprising a capacitor having a high capacitance created by the surface area of the storage electrode of the capacitor, and which method does not require processes which are carried out at high temperatures.
In order to achieve the second object of the present invention, a capacitor including a storage electrode having a side wall formed with a series of prominences and depressions is produced from a sacrificial structure of oxide layers formed at temperatures no higher than 600xc2x0 C.
The capacitor is formed on a substrate having a transistor including a source/drain region. First, an insulating layer is formed over the transistor. A hole is then formed through the insulating layer so as to expose the source/drain region. A first layer of conductive material is then deposited over the substrate to fill the hole. The layer is then planarized so that the insulating layer is exposed and a contact plug is left in the hole. Next, a sacrificial structure comprising a number of oxide layers is formed on the insulating layer including over the contact plug. The oxide layers are each formed by low pressure CVD or plasma enhanced CVD carried out at about 400-600xc2x0 C. Adjacent ones of the oxide layers exhibit different etching rates when exposed to a predetermined etchant. The different etching rates can be the result of differences in the boron or phosphorous content of the layers or of differences in type or concentration of impurities. At least one hole is formed through the sacrificial structure to expose the contact plug, whereby a side wall delimiting the hole is produced. The side wall is etched by the etchant, whereby a series of tooth-like prominences and depressions are formed at the side wall. Then, a conductive material is deposited on the side wall and over the contact plug to form a storage electrode in which the prominences and depressions of the side wall of the sacrificial structure are reproduced. The sacrificial structure is thereafter removed, whereby the conductive material left remaining constitutes the storage electrode of the capacitor. A dielectric material and another layer of conductive material are formed over the storage electrode to complete the capacitor.
In accordance with the present invention, the oxide layers of the sacrificial structure may be formed in a single reaction chamber of a CVD apparatus by varying the gas containing agents of an impurity in successive cycles of operation. Alternatively, the oxide layers may be respectively formed in discrete chambers of a CVD apparatus. Still further, the oxide layers having different types or concentrations of impurities may be respectively formed at different injectors of a gas injection system.
Also, according to the present invention, a silicon HSG layer can be formed on the surface of the storage electrode having the tooth-like prominences and depressions, for further increasing the capacitance of the resultant capacitor. In this method, a protective layer of oxide material is formed over the storage electrode to protect the silicon HSG layer during the process of removing the sacrificial structure.
Each of the oxide layers of the sacrificial structure is formed to a thickness of about 100-1000 xc3x85. Disregarding the time factor involved in the process of manufacturing the sacrificial structure, each of the oxide layers preferably has a thickness of 200 xc3x85. The thinner the oxide layers, the finer the series of prominences and depressions which can be formed at the side wall of the sacrificial structure. In turn, the finer the series of prominences and depressions at the side wall of the sacrificial structure, the finer the series of prominences and depressions at the side wall of the storage electrode and hence, the higher the storage capacitance of the capacitor.
Finally, a silicon HSG layer can be formed on the fine series of prominences and depressions at the side wall of the storage electrode to even further enhance the capacitance level of the capacitor.